1. Field of the Invention
The invention relates to a method for forming bumps.
2. Description of the Prior Art
Flip-chip packaging processes are one of the most popular electronic packaging processes utilized today. In contrast to the some other packaging processes, the dies utilized in flip-chip packaging are not electrically connected to a packaging substrate via a bonding pad through a wire bonding process. Instead, the dies are inverted and solder bumps are utilized to electrically connect and mount the dies onto the packaging substrate. Ideally, flip-chip packaging processes are able to significantly reduce the size of package structures and increase the circuit transmission between the dies and the packaging substrate because no extra wires are required for establishing a connection.
Please refer to FIG. 1 through FIG. 6. FIG. 1 through FIG. 6 are perspective diagrams showing a method for fabricating a bump 10 according to the prior art. As shown in FIG. 1, a substrate 12, such as a wafer having completed internal devices and wirings, is provided. Next, a patterned passivation layer 14 is disposed on the surface of the substrate 12 to expose a plurality of bonding pads 16. Preferably, the bonding pads 16 are composed of copper or aluminum and utilized to electrically connect the internal wires (not shown) within the substrate 12 and the external wires (not shown) located above the packaging substrate.
Next, as shown in FIG. 2, a series of sputtering, deposition, and etching process are performed to form an under bump metallurgy layer 18 on each of the bonding pads 16 and the passivation layer 14. The under bump metallurgy layer 18 is composed of aluminum, nickel vanadium, and copper or titanium, nickel vanadium, and copper. As shown in FIG. 3, a photoresist 20 is formed on the substrate 12 and covering the passivation layer 14. Preferably, the photoresist 20 is composed of a dry film photoresist or a liquid type photoresist.
As shown in FIG. 4, an exposure process and a development process are performed to pattern the photoresist 20 and form a plurality of openings 22 within the photoresist 20, in which the openings 22 expose the under bump metallurgy layer 18 above each of the bonding pads 16. An electroplating process is performed thereafter to deposit a solder 24 composed of copper into each of the openings 22.
After stripping the photoresist 20, as shown in FIG. 5, an etching process is performed by using the solder 24 as a mask with an etchant composed of nitric acid, acetic acid, phosphoric acid, hydrogen peroxide, hydrochloric acid, and sulfuric acid to remove a portion of the under bump metallurgy layer 18 disposed on the passivation layer 14. Next, as shown in FIG. 6, a reflow process is performed to form a plurality of bumps 10 on the bonding pads 16.
However, the solder 24, being composed of copper, is often corroded by the etchant used for etching the under bump metallurgy layer 18, thus resulting in a state vulnerable for oxidation. The affected solder 24 not only shows a poor electrical performance, but also causes a composition shift for the bumps 10 formed afterwards. The composition shift of the bumps 10 ultimately influences the yield and reliability of other devices connecting to the bumps.